The present invention generally relates to semiconductor process, and more specifically, to a planarizeation process
With the progressing of semiconductor technology into the ULSI (Ultra Large Scale Integration) stage, the integrity of semiconductor devices has increased significantly. A single integrated circuits (IC) chip may includes millions or even billions of devices. The devices like transistors, capacitors and the elements like connections and isolations must be made much smaller for a densely packed IC chip. A great number of challenges like lithography, etching, and planarization process must be improved for fabricating integrated circuits with sub-micrometer or even smaller feature sizes.
In the front-end process of fabricating integrated circuits, an active area is defined. On a wafer, a plurality of active areas are made. Generally, there are some methods of defining active areas, including of surrounding each active area by forming a layer of field oxide, or surrounding each active area by forming some shallow trenches. So as the present manufacturing technology for IC, the method of defining active areas by forming oxide layers needs so many areas that the integrity of IC can not promote. As a result, the shallow trench isolation (STI) technique is now the most popular isolation technique.
The shallow trench isolation technique is about to form shallow trenches within the substrate first, and then to fill with oxide layer as a non-conducting material. A planarization step is performed to remove the oxide deposited on the top of the active areas to form shallow trenches with a planarized surface. A further description is set forth below with the accompanying drawings.
Referring now to FIG. 1, a pad oxide 110 is formed on the surface of a substrate 100, while a silicon nitride layer 120 is then deposited on the pad oxide 110, using a proper CVD method, such as plasma enhanced CVD, as a stop layer of a polishing or an etching process to avoid destroying the substrate 100. After the pad oxide 110 and the silicon nitride 120 are formed, use traditional lithographic and etching processes to form a patterned photoresist layer (not shown) thereon and then etch away the nitride layer 120 using the patterned PR. The remained nitride layer 120 is thus utilized as the mask for further etching the substrate 100 to generate a plurality of shallow trenches. The shallow trenches are the non-active areas, while the regions between the shallow trenches are the active areas. Specifically, due to different designs of ICs, the widths of the active and the non-active areas are different.
Referring to FIG. 2, a process of forming a liner oxide on the side wall and the bottom of shallow trenches by means of, for example, thermal oxidization method. Moreover, a layer of silicon oxide 130 is then formed on the shallow trenches of the non-active areas and on the nitride layer 120 of the active areas using high density plasma CVD (HDPCVD). HDPCVD method is to utilize reaction gases, including silane, oxygen and argon, etc., in the reaction chamber to generate inductively coupled plasma for higher density. However, the thickness of deposited films, according to the HDPCVD, is not regular over the surface. More specifically, the speed of films deposited on side walls is much slower than that on planar surfaces. If the widths of trenches are different, the thin films deposited by HDPCVD can fill narrower trenches more easier. Because of pattern of the bottom layer, the surface topography of the silicon oxide layer 130 is rough and uneven, concave on shallow trench regions, convex on the nitride layer 120.
After the silicon oxide layer 130 is deposited, the oxide layer 130 above the nitride layer 120 must be removed to get a planarized surface for subsequent processes. The promising technique for global planarization is chemical mechanical polishing (CMP) process or a mixed process of both CMP and etching processes. Although the CMP technique is an effective method for planarization, the time needed is hard to find out and control.
During the STI process described above, the time of the CMP process should be controlled precisely. However, according to the characteristic of the CMP process, the polishing speed is relevant to the bottom pattern, i.e., the larger area required for polishing, the smaller polishing speed it would be, and vice versa. That is the speed over the wafer surface is not equal. As a result, some regions on the wafer are over polished, while some are under polished.
Generally, the traditional technique for controlling the polishing time is to utilize an optical measurement apparatus to measure the thickness of a specific region, such as a process control and monitor key (PCM key), on the wafer surface, while a CMP process is performed, for determining the endpoint for material removal in a specific layer thickness. More specifically, the PCM key is one specific region, for monitoring, on the wafer surface, containing the same structure and thickness of films, but without any circuit pattern thereon. Accordingly, the PCM key""s surface is planar and smooth, as illustrated in FIGS. 3A and 3B. FIG. 3A is the top view of the PCM key, while FIG. 3B is the cross-sectional diagram of the PCM key. However, an error is easily made as simulating the thickness variation of the films, on the wafer by monitoring the planar PCM key""s topography surface of the device regions. This is because that the polishing speed on the PCM key is slower than that on the device regions. When an endpoint in the films of the PCM key has been detected, the films of the corresponding device regions are often over polished. The certain damages on the device regions will result in function degradation thereof.
Moreover, generally, the traditional CMP process should discover each proper polishing time for each wafer with different pattern by means of doing experiments. It is understood that the CMP process is such a product-dependant process. As a result, there is an essential need to precisely control and monitor the polishing speed and time in the CMP process to improve the planarization process of semiconductor wafers and further to enhance their yield and throughput.
It is an objective of this invention to provide a method of controlling and monitoring the thickness variation of the film structure of the semiconductor wafer.
It is another objective of this invention to provide a planarization process to precisely control the stop layer in the chemical mechanical polishing process.
According to objectives mentioned above, the invention discloses a method of planarization process of a semiconductor wafer by controlling and monitoring the thickness variation of the film structure of the testing region thereon. The planarization method comprises the following processes. First, calculate a pattern density of the film structure of the device region. Etch the film structure of the testing region with a pattern density of the film structure of the testing region substantially compatible with that of the device region. Finally, polish the semiconductor wafer and monitor the thickness variation of the film structure of the testing region in order to precisely control the speed or time of polishing the whole wafer and to make sure the polishing process ended on the stop layer of the device region.